Electrostatic clamps or chucks (ESCs) are often utilized in the semiconductor industry for clamping workpieces or substrates during plasma-based or vacuum-based semiconductor processes such as ion implantation, etching, chemical vapor deposition (CVD), etc. Clamping capabilities of the ESCs, as well as workpiece temperature control, have proven to be quite valuable in processing semiconductor substrates or wafers, such as silicon wafers. A typical ESC, for example, comprises a dielectric layer positioned over a conductive electrode, wherein the semiconductor wafer is placed on a surface of the ESC (e.g., the wafer is placed on a surface of the dielectric layer). During semiconductor processing (e.g., ion implantation), a clamping voltage is typically applied between the wafer and the electrode, wherein the wafer is clamped against the chuck surface by electrostatic forces.
A subset of electrostatic clamps, referred to as Johnsen-Rahbek (J-R) clamps, utilize “leaky” dielectric layers (e.g., semiconductive dielectric layers having bulk resistances of between approximately 1×108 to 1×1012 Ohm-cm) in contact with the wafer, wherein greater clamping forces can be achieved at lower voltages than with conventional non-J-R clamps. Typically, lower voltage input to the ESC not only reduces power supply requirements associated with the J-R clamps, but further provides a clamping environment that is potentially less destructive to the wafer and devices formed thereon.
A conventional J-R clamp, for example, comprises a dielectric layer that is slightly conductive, thus generally permitting a thickness of the dielectric layer (e.g., a ceramic) to be much thicker than would be permitted for a “classic” or Coulombic ESC. Such an increase in thickness greatly facilitates the clamp manufacturing process, while also reducing clamp operating voltages. For example, the dielectric layer can be used as a base for the formation of positive and negative electrodes by screen printing and firing of a dielectric paste. However, a charge transfer typically resulting from the use of a semiconductor dielectric, for example, can also transmit a charge to the wafer, therein generating residual clamping forces that can result in a delay in releasing the wafer from the clamp. To mitigate the effects of residual clamping forces, A/C clamping voltages utilizing multiple groups of electrodes (e.g., multi-phasing or poly-phasing) can be used. However, such A/C clamping voltages and multiple groups of electrodes typically necessitate that each electrode have its area distributed somewhat evenly across the clamp. The resulting electrode structures can be quite complicated because of the design constraints driven by the need to maximize clamping area and force.
Some conventional ESCs further utilize backside gas cooling in order to cool the workpiece during processing. In such instances, a cooling gas is presented between the workpiece and a surface of the ESC, wherein the pressure of the gas is generally proportional to the heat transfer-coefficient thereof. Thus, in order to attain a higher cooling rate, a higher backside cooling gas pressure is typically needed in order to provide the desired thermal performance. Thus, in order to maintain proper clamping of the workpiece, forces associated with the higher backside gas pressure should be properly offset with a larger clamping force or voltage applied to the ESC. In cases of high power ion implantations (e.g., 2.5 kW), the gas pressure is substantially high in order to attain proper cooling, wherein the clamping force should be appropriately increased in an attempt to compensate for the substantially high gas pressure. Further, in the case of a two-dimensionally scanned workpiece, such as seen in some ion implantation systems, large G-forces can be present during workpiece oscillation, wherein even higher clamping forces are necessitated in order to maintain sufficient contact between the workpiece and the ESC. However, increasing the clamping force on the entire workpiece can have deleterious effects, such as increased particulate contamination, since the increased clamping pressure can cause frictional forces between the ESC and the workpiece across the surface of the workpiece, thus leading to greater chances of particulate contamination across the areas of the workpiece in which devices are formed.
Furthermore, design parameters such as backside cooling gas pressure, process chamber pressure, and desired clamping force are typically tightly coupled, such as in the case of the two-dimensionally scanned ion implantation system, wherein ion transport efficiencies associated with operating pressures and backside cooling gas leakage also come into play. Thus, offsetting the clamping pressure with gas pressure, and vice versa, can be quite difficult in such a tightly coupled system.
Therefore, a need exists in the art for a multiple-electrode clamp that generally de-couples the clamping force needed to clamp the workpiece from the requirements associated with backside gas cooling, wherein particulate contamination can be generally mitigated, while providing the desired temperature uniformity and clamping pressure for efficiently processing the workpiece.